1. Field of the Invention
The present invention relates in general to switched-capacitor techniques and in particular to switched-capacitor summer circuits and methods and systems using the same.
2. Description of the Related Art
Delta-sigma modulators are particularly useful in digital to analog and analog to digital converters (DACs and ADCs). Using oversampling, the delta-sigma modulator spreads the quantization noise power across the oversampling frequency band, which typically much greater than the input signal bandwidth. Additionally, the delta sigma modulator performs noise shaping by acting as a lowpass filter to the input signal and a highpass filter to the noise; most of the quantization noise power is thereby shifted out of the signal band.
The typical delta sigma modulator includes a summer summing the input signal with negative feedback, a linear filter, quantizer and a feedback loop with a digital to analog converter coupling the quantizer output and the inverting input of the summer. In a first order modulator, the linear filter comprises a single integrator stage while the filter in higher a order modulator comprises a cascade of a corresponding number of integrator stages. The quantizer can be either a one-bit or a multiple-bit quantizer.
In the case of a higher-order multiple-bit modulator with weighted feed-forward summation, the outputs of the integrator stages are passed to a summation circuit. This summation circuitry does not have a xe2x80x9cmemory.xe2x80x9d In other words, this circuitry must be reset to zero after each summation operation, even though the integrator outputs typical only increment up or down in voltage by a small amount with each new sample. Consequently, the summation circuitry must handle relatively large voltage swings, especially when the integrator outputs approach their maximum values. Moreover, when the summation circuitry includes an operational amplifier, a large tail current is required to achieve a sufficiently large output slew rate.
The principles of the present invention and embodied in switched-capacitor summation techniques. According to one such embodiment, a switched-capacitor summer is disclosed which includes an operational amplifier having an input and an output, first and second parallel capacitors, and first switching circuitry. The first switching circuit discharges the first capacitor during a first timing phase and couples the first capacitor between the input and the output of operational amplifier during a second timing phase. The second switching circuit couples the second capacitor between the input and output of operational amplifier during the first phase to maintain a voltage at the operational amplifier output and charges the second capacitor during the second phase.
The principles of the present invention allow for the construction and operation of summation circuits which are faster and consume less power. In particular, according to the inventive concepts, hold up capacitors and associated switching circuitry are provided such that the summer output voltage can be maintained while the conventional feedback capacitors are reset after each summation operation.